PIC16F627A-I/P【PDF 17/180 页】IC MCU FLASH 1KX14 EEPROM 18DIP

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2009 Microchip Technology Inc.

DS40044G-page 113

PIC16F627A/628A/648A

14.8.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

External Reset input on MCLR pin

Watchdog Timer wake-up (if WDT was enabled)

Interrupt from RB0/INT pin, RB port change, or

any peripheral interrupt, which is active in Sleep.

The first event will cause a device Reset. The two latter

events are considered a continuation of program

execution. The TO and PD bits in the Status register

can be used to determine the cause of device Reset.

PD bit, which is set on power-up, is cleared when Sleep

is invoked. TO bit is cleared if WDT wake-up occurred.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the

interrupt address (0004h). In cases where the

execution of the instruction following SLEEP is not

desirable, the user should have an NOP after the SLEEP

instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

FIGURE 14-17:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

14.9

Code Protection

With the Code-Protect bit is cleared (Code-Protect

enabled), the contents of the program memory

locations are read out as ‘0’. See “PIC16F627A/628A/

648A EEPROM Memory Programming Specification

”

(DS41196) for details.

14.10 User ID Locations

Four memory locations (2000h-2003h) are designated

as user ID locations where the user can store

checksum or other code-identification numbers. These

locations are not accessible during normal execution

but are readable and writable during Program/Verify.

Only the Least Significant 4 bits of the user ID locations

are used for checksum calculations although each

location has 14 bits.

Note:

If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the corresponding

interrupt flag bits set, the device will not enter

Sleep. The SLEEP instruction is executed as

a NOP instruction.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2

0004h(3)

0005h

Dummy cycle

TOST(1,2)

PC + 2

Note

XT, HS or LP Oscillator mode assumed.

TOST = 1024 TOSC (drawing not to scale). Approximately 1

μs delay will be there for RC Oscillator mode.

GIE = 1 assumed. In this case, after wake-up the processor jumps to the interrupt routine. If GIE = 0, execution will continue

in-line.

CLKOUT is not available in these Oscillator modes, but shown here for timing reference.

Note:

Only a Bulk Erase function can set the CP

and CPD bits by turning off the code

protection. The entire data EEPROM and

Flash program memory will be erased to

turn the code protection off.

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